-- "blowfishvhdl" is a free synthesizable VHDL Blowfish implementation
-- Copyright (C) 2000  Wesley J. Landaker <wjl@mindless.com>

-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.

-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.

-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

-- See http://blowfishvhdl.sourceforge.net for more information.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity tb_blowfish is
end tb_blowfish;

architecture fishy of tb_blowfish is

  component blowfish is
  port (
    clk  : in std_logic;

    key      : in  std_logic_vector(447 downto 0);
    key_size : in  std_logic_vector(3 downto 0);  -- key size in 32-bit chunks

    data_in  : in  std_logic_vector(63 downto 0);
    data_out : out std_logic_vector(63 downto 0);

    new_key  : in bit;
    new_data : in bit;

    encrypt  : in bit;

    ready    : out bit
  );
  end component; 

  signal clk : std_logic := '0';
  signal key : std_logic_vector(447 downto 0);
  signal key_size : std_logic_vector(3 downto 0);
  signal data_in, data_out : std_logic_vector(63 downto 0);
  signal new_key, new_data, encrypt, ready : bit;
  
begin

  bf: blowfish port map(clk,key,key_size,data_in,data_out,new_key,
                        new_data,encrypt,ready);


  clk <= not(clk) after 50 ns;

  process
  begin
    wait until clk'event and clk = '1'; 
    wait until clk'event and clk = '1';
    key <= x"8761237da6945454fac87e2143149879e8ff40bdbd3ddd764ed4f2ae786987c698987911234e9879e8ffdbdbdbd78bf62456cefda9876876";
    key_size <= x"e";                       -- we'll just assume 448 bits
    data_in <= x"1234567890abcdef";
    new_key <= '1';
    new_data <= '0';
    encrypt <= '1';
    wait until clk'event and clk = '1';
    new_key <= '0';
    wait until ready'event and ready = '1';  -- wait for key initialization
    new_data <= '1';
    wait until clk'event and clk = '1';
    new_data <= '0';
    wait until ready'event and ready = '1';  -- wait for encrypt to end
    data_in <= data_out;
    new_data <= '1';
    encrypt <= '0';
    wait until clk'event and clk = '1';
    new_data <= '0';
    wait until ready'event and ready = '1';
  end process;

end fishy;