-- "blowfishvhdl" is a free synthesizable VHDL Blowfish implementation
-- Copyright (C) 2000  Wesley J. Landaker <wjl@mindless.com>

-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.

-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.

-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

-- See http://blowfishvhdl.sourceforge.net for more information.


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity parray_init is
port (
  keychunk : in  std_logic_vector(31 downto 0); 
  address  : in  std_logic_vector(4 downto 0);
  data     : out std_logic_vector(31 downto 0)
);
end parray_init;

architecture fishy of parray_init is
  -- since we only have 18 data elemnts, we'll brute force this
  -- the sboxes, on the other hand, will have to be more elegant
  signal data0  : std_logic_vector(31 downto 0);
  signal data1  : std_logic_vector(31 downto 0);  
  signal data2  : std_logic_vector(31 downto 0);  
  signal data3  : std_logic_vector(31 downto 0);  
  signal data4  : std_logic_vector(31 downto 0);  
  signal data5  : std_logic_vector(31 downto 0);  
  signal data6  : std_logic_vector(31 downto 0);  
  signal data7  : std_logic_vector(31 downto 0);  
  signal data8  : std_logic_vector(31 downto 0);  
  signal data9  : std_logic_vector(31 downto 0);  
  signal data10 : std_logic_vector(31 downto 0);  
  signal data11 : std_logic_vector(31 downto 0);  
  signal data12 : std_logic_vector(31 downto 0);  
  signal data13 : std_logic_vector(31 downto 0);  
  signal data14 : std_logic_vector(31 downto 0);  
  signal data15 : std_logic_vector(31 downto 0);  
  signal data16 : std_logic_vector(31 downto 0);  
  signal data17 : std_logic_vector(31 downto 0);

  signal data_raw : std_logic_vector(31 downto 0);       
  
begin

  data0  <= x"243f6a88";
  data1  <= x"85a308d3";
  data2  <= x"13198a2e";
  data3  <= x"03707344";
  data4  <= x"a4093822";
  data5  <= x"299f31d0";
  data6  <= x"082efa98";
  data7  <= x"ec4e6c89";
  data8  <= x"452821e6";
  data9  <= x"38d01377";
  data10 <= x"be5466cf";
  data11 <= x"34e90c6c";
  data12 <= x"c0ac29b7";
  data13 <= x"c97c50dd";
  data14 <= x"3f84d5b5";
  data15 <= x"b5470917";
  data16 <= x"9216d5d9";
  data17 <= x"8979fb1b";

  with address select data_raw
    <= data0  when b"00000",
       data1  when b"00001",
       data2  when b"00010",
       data3  when b"00011",
       data4  when b"00100",
       data5  when b"00101",
       data6  when b"00110",
       data7  when b"00111",
       data8  when b"01000",
       data9  when b"01001",
       data10 when b"01010",
       data11 when b"01011",
       data12 when b"01100",
       data13 when b"01101",
       data14 when b"01110",
       data15 when b"01111",
       data16 when b"10000",
       data17 when others;

  data <= data_raw xor keychunk;
  
end;