-- "blowfishvhdl" is a free synthesizable VHDL Blowfish implementation
-- Copyright (C) 2000  Wesley J. Landaker <wjl@mindless.com>

-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.

-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.

-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

-- See http://blowfishvhdl.sourceforge.net for more information.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity parray is
port (
  clk : in std_logic;
 
  address  : in  std_logic_vector(4 downto 0);
  data_in  : in  std_logic_vector(31 downto 0);
  data_out : out std_logic_vector(31 downto 0);

  we : in bit
);
end parray;

architecture fishy of parray is
  -- since we only have 18 data elemnts, we'll brute force this
  -- the sboxes, on the other hand, will have to be more elegant
  signal data0  : std_logic_vector(31 downto 0);
  signal data1  : std_logic_vector(31 downto 0);  
  signal data2  : std_logic_vector(31 downto 0);  
  signal data3  : std_logic_vector(31 downto 0);  
  signal data4  : std_logic_vector(31 downto 0);  
  signal data5  : std_logic_vector(31 downto 0);  
  signal data6  : std_logic_vector(31 downto 0);  
  signal data7  : std_logic_vector(31 downto 0);  
  signal data8  : std_logic_vector(31 downto 0);  
  signal data9  : std_logic_vector(31 downto 0);  
  signal data10 : std_logic_vector(31 downto 0);  
  signal data11 : std_logic_vector(31 downto 0);  
  signal data12 : std_logic_vector(31 downto 0);  
  signal data13 : std_logic_vector(31 downto 0);  
  signal data14 : std_logic_vector(31 downto 0);  
  signal data15 : std_logic_vector(31 downto 0);  
  signal data16 : std_logic_vector(31 downto 0);  
  signal data17 : std_logic_vector(31 downto 0);  
begin
  
  process(clk,we,address,data_in,data0,data1,data2,data3,data4,data5,data6,
          data7,data8,data9,data10,data11,data12,data13,data14,data15,data16,
          data17)
  begin
    if (clk'event and clk = '1') then
      if (we = '1') then
        case address is
          when b"00000" => data0  <= data_in;
          when b"00001" => data1  <= data_in;
          when b"00010" => data2  <= data_in;
          when b"00011" => data3  <= data_in;
          when b"00100" => data4  <= data_in;
          when b"00101" => data5  <= data_in;
          when b"00110" => data6  <= data_in;
          when b"00111" => data7  <= data_in;
          when b"01000" => data8  <= data_in;
          when b"01001" => data9  <= data_in;
          when b"01010" => data10 <= data_in;
          when b"01011" => data11 <= data_in;
          when b"01100" => data12 <= data_in;
          when b"01101" => data13 <= data_in;
          when b"01110" => data14 <= data_in;
          when b"01111" => data15 <= data_in;
          when b"10000" => data16 <= data_in;
          when b"10001" => data17 <= data_in;
          when others   => null;
        end case;
      else -- we = '0'
        case address is
          when b"00000" => data_out<= data0;
          when b"00001" => data_out<= data1;
          when b"00010" => data_out<= data2;
          when b"00011" => data_out<= data3;
          when b"00100" => data_out<= data4;
          when b"00101" => data_out<= data5;
          when b"00110" => data_out<= data6;
          when b"00111" => data_out<= data7;
          when b"01000" => data_out<= data8;
          when b"01001" => data_out<= data9;
          when b"01010" => data_out<= data10;
          when b"01011" => data_out<= data11;
          when b"01100" => data_out<= data12;
          when b"01101" => data_out<= data13;
          when b"01110" => data_out<= data14;
          when b"01111" => data_out<= data15;
          when b"10000" => data_out<= data16; 
          when b"10001" => data_out<= data17;
          when others   => null;
        end case;
      end if; -- we
    end if; -- clk
  end process;

end;